An electric traction drive, such as may be used in an electric or hybrid vehicle, requires high voltage utilization to produce torque as efficiently as possible within a constrained volume and weight. For such high voltage utilization, an electric drive system may operate with an overmodulation processor for a pulse width modulator (PWM) that includes a six-step mode (described below). FIG. 1 is a schematic representation of a known current regulator and control architecture 100 for a multiphase AC motor 102.
Architecture 100 includes a PWM inverter 104 that drives AC motor 102 over a connection arrangement 106, which may include any number of connection lines. The number of connections represented by connection arrangement 106 is defined by the number of phases used in AC motor 102. For example, a three-phase AC motor 102 would have three connection lines. Connection arrangement 106 may include or be coupled to current sensors 108. The number of current sensors 108 is again defined by the number of phases used in AC motor 102. The outputs of current sensors 108 are coupled to a transformation processor 110 using connection lines 112. The number of connection lines 112 is again defined by the number of phases used in AC motor 102, in this example, three.
The three phase currents (ias, ibs, and ics) that are measured by current sensors 108 typically carry sinusoidal current waveforms when viewed in a reference frame synchronous with the stator of the AC motor 102, the stationary frame. In transformation processor 110, these three phase currents are transformed into the synchronous d-q frame using equation (1) as follows:
                              [                                                                      i                  ds                  r                                                                                                      i                  qs                  r                                                              ]                =                                            T              ⁡                              (                                  θ                  r                                )                                      ⁡                          [                                                                                          i                      as                                                                                                                                  i                      bs                                                                                                                                  i                      cs                                                                                  ]                                =                                                    2                3                            ⁡                              [                                                                                                    cos                        ⁡                                                  (                                                      θ                            r                                                    )                                                                                                                                    cos                        (                                                                              θ                            r                                                    -                                                                                    2                              3                                                        ⁢                            π                                                                          )                                                                                                            cos                        (                                                                              θ                            r                                                    +                                                                                    2                              3                                                        ⁢                            π                                                                          )                                                                                                                                                -                                                  sin                          ⁡                                                      (                                                          θ                              r                                                        )                                                                                                                                                              -                                                  sin                          (                                                                                    θ                              r                                                        -                                                                                          2                                3                                                            ⁢                              π                                                                                )                                                                                                                                    -                                                  sin                          (                                                                                    θ                              r                                                        +                                                                                          2                                3                                                            ⁢                              π                                                                                )                                                                                                                    ]                                      ⁡                          [                                                                                          i                      as                                                                                                                                  i                      bs                                                                                                                                  i                      cs                                                                                  ]                                                          (        1        )            
In equation (1), the rotor angle θr is the electrical rotor position calculated from the mechanical rotor position and the motor pole number. The rotor angle θr is measured by a sensor (not shown). The d-q frame of reference, in Cartesian coordinates, is synchronous with the rotation of the electrical rotor position θr.
As used herein, the meaning of subscription and superscription is as follows.
Subscript a, b, and c: Quantity in the phase a, b, and c.
Subscript d and q: Quantity in the d-q frame.
Subscript s: Quantity of stator windings.
Superscript s: Quantity in the stationary frame.
Superscript r: Quantity in the rotating (synchronous) frame.
Superscript *: Quantity which is commanded.
The signals are referenced to the d-q reference frame as the signals are processed through a synchronous frame current regulator 114 and through command voltage limiters 116/118, and the processed signals are reconverted into a stator reference frame in a rotational transformation processor 120.
The outputs of transformation processor 110 are the measured d-q currents idsr and iqsr as depicted in FIG. 1. The measured d-q currents (idsr and iqsr) are coupled to synchronous frame current regulator 114. In particular, the measured d current (idsr) is coupled to the d proportional integrating (PI) regulator 122, and the measured q current (iqsr) is coupled to the q PI regulator 124. In addition, commanded d-q currents (idsr* and iqsr*) are coupled to respective d and q PI regulators 122/124 over respective connection lines 126/128 from a higher level controller (e.g., a torque or a speed controller). Clamped voltage commands (Vds—outr* and Vqs—outr*) output from the respective command voltage limiters 116/118 are fed back into respective d and q PI regulators 122/124.
Feed forward voltages (Vds—FFr and Vqs—FFr) are provided to respective d and q PI regulators 122/124 over respective connection lines 130/132. These feed forward voltages are typically provided by the current controller, speed controller, or torque controller based on the motor speed, motor parameters and the currents drawn by the motor. The command output voltages of d and q PI regulators 122/124 are coupled to command voltage limiters 116/118, discussed below with respect to FIG. 3.
The clamped voltage commands (Vds—outr* and Vqs—outr*) output from command voltage limiters 116/118 are coupled to rotational transformation processor 120 to transform the voltage in the synchronous frame to the voltage in a stationary frame in which the command voltages rotate as follows.
                              [                                                                      v                  ds_out                                      s                    *                                                                                                                        v                  qs_out                                      s                    *                                                                                ]                =                                            R              ⁡                              (                                  θ                  r                                )                                      ⁡                          [                                                                                          v                      ds_out                                              r                        *                                                                                                                                                        v                      qs_out                                              r                        *                                                                                                        ]                                =                                    [                                                                                          cos                      ⁡                                              (                                                  θ                          r                                                )                                                                                                                        -                                              sin                        ⁡                                                  (                                                      θ                            r                                                    )                                                                                                                                                                                sin                      ⁡                                              (                                                  θ                          r                                                )                                                                                                                        cos                      ⁡                                              (                                                  θ                          r                                                )                                                                                                        ]                        ⁡                          [                                                                                          v                      ds_out                                              r                        *                                                                                                                                                        v                      qs_out                                              r                        *                                                                                                        ]                                                          (        2        )            
The d and q outputs from rotational transformation processor 120 are coupled to an overmodulation processor 134 (a processor that includes six step mode). The rotated voltage command (Vds—outs* and Vqs—outs*), which rotates in the stationary reference frame, is processed by the overmodulation processor 134. If the magnitude of the command voltage (Vds—outs* and Vqs—outs*) is less than
            1              3              ⁢          V      dc        ,which is the maximum voltage of linear space vector PWM, the voltage is not modified by overmodulation processor 134. If the magnitude is larger than
            1              3              ⁢          V      dc        ,the inverter cannot realize the commanded phase and magnitude of the voltage due to the physical limitation of the inverter. In that case, overmodulation processor 134 modifies the phase and/or magnitude of the clamped output voltage into the modified voltage (Vds—ovs* and Vqs—ovs*), whose fundamental component magnitude and phase matches with those of the command voltage (Vds—outs* and Vqs—outs*) in steady state. When the voltage magnitude is larger than
            1              3              ⁢          V      dc        ,the PWM inverter 104 can not synthesize the instantaneous phase and magnitude of the command voltage due to its physical limitations. However, the fundamental component of the PWM output voltage will be the same as the command voltage, owing to the function of the overmodulation process. There are many overmodulation methods, which realize the fundamental component of the commanded voltage up to six-step PWM.
The outputs of overmodulation processor 134 are coupled to an inverse transformation processor 136. Inverse transformation processor 136 converts a stationary frame representation of a rotating voltage command from the overmodulation processor 134 into a three phase sinusoid notation of the voltage command as follows.
                              [                                                                      v                  as                  *                                                                                                      v                  bs                  *                                                                                                      v                  cs                  *                                                              ]                =                                                            T                ⁡                                  (                  0                  )                                                            -                1                                      ⁡                          [                                                                                          v                      ds_ov                                              s                        *                                                                                                                                                        v                      qs_ov                                              s                        *                                                                                                        ]                                =                                    [                                                                    1                                                        0                                                                                                              -                                              1                        2                                                                                                                        +                                                                        3                                                2                                                                                                                                                        -                                              1                        2                                                                                                                        -                                                                        3                                                2                                                                                                        ]                        ⁡                          [                                                                                          v                      ds_ov                                              s                        *                                                                                                                                                        v                      qs_ov                                              s                        *                                                                                                        ]                                                          (        3        )            
The outputs of inverse transformation processor 136 are coupled to PWM inverter 104, which drives AC motor 102.
FIG. 2 depicts an example of d-axis PI regulator 122. The q-axis PI regulator 124 operates in the same way. In FIG. 2, PI regulator 122 includes four summation points (reference numbers 152, 154, 156, and 158), three multiplier constants (reference numbers 162, 164, and 166), and an integrator 168. Summation point 152 forms the d-axis current error (ids—errr) as a difference between the commanded d current (idsr*) and the measured d current (idsr). The d-axis current error (ids—errr) from the difference output of summation point 152 is multiplied by the proportional gain constant (Kpd) at 166, and the multiplied value is one of three values summed at summation point 156. The voltage command (Vdsr*), output from summation point 156, will minimize the current error (ids—errr) and is input into command voltage limiter 116. The d-axis output of command voltage limiter 116, depicted in FIG. 1, is subtracted at summation point 158 from the voltage command (Vdsr*). The voltage difference output of summation point 158 is multiplied at element 162 by the anti-windup gain (Kad), and the multiplied value is subtracted from the d-axis current error (ids—errr) at summation point 154. The difference output of summation point 154 is multiplied at element 164 by the integral gain (Kid), the multiplied value is integrated by integrator 168, and the integrated value output from integrator 168 is another of the three values summed at summation point 156. The output of the current regulator (i.e., the integrated value output from integrator 168 and the output of summation point 152 scaled by the proportional gain constant (Kpd) at element 166) are added to the feed-forward voltage (Vds—FFr) at summation point 156 to generate the voltage command (Vdsr*).
FIG. 3 is a schematic representation of command voltage limiters 116/118. In FIG. 3, the command voltage limiters 116/118 are two separate but identical voltage limiters that serve to limit the respective input voltages (Vdsr* and Vqsr*). The command voltage output (Vds—outr* and Vqs—outr*) of each limiter 116/118 is limited between ±VdMAXr and ±VqMAXr, respectively.
In known systems, the current regulation performance degrades when the inverter operates with the overmodulation processor beyond the linear PWM area, discussed above. This degradation is because the instantaneous output voltage of the current regulator is modified by the overmodulation processor to be constrained within the physical limitation of the inverter. When a current error is caused by this voltage constraint, the integrator of the PI regulator is subject to saturation, and the saturation produces a large overshoot or undershoot. This is called the windup phenomena of the PI regulator. The role of anti-windup control is to prevent the windup phenomena during the voltage clamping. When the output voltage is clamped frequently, the anti-windup control is very important to prevent windup of the PI regulator and to maintain current control performance.